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LTC6994-1/LTC6994-2
18
699412fb
applicaTions inForMaTion
Settling Time
Following a 2
× or 0.5× step change in ISET, the out-
put delay takes approximately six master clock cycles
(6 tMASTER) to settle to within 1% of the final value.
An example is shown in Figure 12, using the circuit in
Figure 10.
Figure 12. Typical Settling Time
VCTRL
2V/DIV
IN
5V/DIV
OUT
5V/DIV
DELAY
2s/DIV
LTC6994-1
V+ = 3.3V
DIVCODE = 0
RSET = 200k
RMOD = 464k
tOUT = 3s AND 6s
20s/DIV
699412 F12
Coupling Error
The current sourced by the SET pin is used to bias the
internal master oscillator. The LTC6994 responds to
changesinISETalmostimmediately,whichprovidesexcel-
lent settling time. However, this fast response also makes
the SET pin sensitive to coupling from digital signals, such
as the IN input.
Even an excellent layout will allow some coupling between
IN and SET. Additional error is included in the specified
accuracy for NDIV = 1 to account for this. Figure 13 shows
that ÷1 supply variation is dependent on coupling from
rising or falling inputs.
A very poor layout can actually degrade performance
further. The PCB layout should avoid routing SET next to
IN (or any other fast-edge, wide-swing signal).
SUPPLY (V)
2
–1.0
0
0.4
0.2
0.6
0.8
1.0
4
5
6
–0.4
–0.2
–0.6
–0.8
3
699412 F13
DRIFT
(%)
FALLING EDGE DELAY
RISING EDGE DELAY
RSET = 50k
NDIV = 1
Figure 13. Delay Drift vs Supply Voltage
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